Basics of Digital Electronics, Logic Design, Computer Architecture, FPGA, Verilog, SystemVerilog, UVM, some communication/bus protocols, Projects explanation.
Design Verification Engineer Interview Questions
3,713 design verification engineer interview questions shared by candidates
question about Logic design FIFO related questions were asked: what requirements will be needed from designer, what will be the test points, coverage points, assertion checks Regarding Technical skills I don't have any difficulties and regarding job location to change from Bangalore can be difficult Few puzzles and Projects in my resume
Are you open to relocation
Virtual Memories..
how does fork-join,join_any etc work
What is the circuit of a full adder?
they give me a code in assembly , was a problem in the code and I asked to fined the problem
Make a counter design with code
Ques. Introduction and previous work Ques. 5 stage pipeline design and verification Ques. branch predictor Ques. system verilog Ques. Optimize program for pair of numbers with fixed sum value.
Design a system to test a memory device integrity over time.
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