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Design Verification Interview Questions
3,719 design verification interview questions shared by candidates
Edge trigger variation coding in RTL
Q: How do you construct a 4x1 MUX using 2x1 MUXs
1)data should be <20, this was the constraint existed, but you should make the data in range 30 to 40 without using constraint_mode. 2) what the uses of bins in coverage
We want to send a specific amount of data and to prevent errors, we want to divide the data into several segments randomly within a certain size range. How can we perform this division so that there will definitely be enough data for all the remaining packets?
first was an assembly question, to implement multiplication with certain commands and few registers avaliable. second question was to build a xor gate with 4 wierd components which are sometimes Z and sometimes have output.
CDC, HW design, testbench engineering, etc..
Had to write a verilog code for some handshaking protocol.
Setup/hold time problem; meta-stability; 5-stage pipeline
Implement a circuit board the receives an 8-bit bus. The output is an 8-bit bus where the first net that is '1' in the input is also '1' in the output, the rest are '0' (in other words - "find first '1' in the input bus).
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