Based in UVM and System verilog and project related questions
Design Verification Interview Questions
3,719 design verification interview questions shared by candidates
1. Describe your current project, contribution and team structure? 2. Write Read and write transactions timing diagram of APB bus. With and without wait states? 3. Find the second largest in the integer array with single iteration. 4. Given a character array of 1000 elements, how do you find, how many times each of the character is repeated? 5. If there is any digital wave coming with random 0s and 1s, how do you find the time difference between 2 successive 1s? 6. Write full & empty conditions for FIFO. What are the verification scenarios of Asynchronous FIFO. 7. Behavioral questions related to personality and team.
What do you like to do in your free time?(yeah)
Logical and analytical question. Test will be taken on hackerrank.
-how do you keep yourself motivated? -tell me about a weakness you have -tell me about a mistake you've done and many more.
¿Cual es tu rutina en un día normal?
How my experience is related to the job description.
The interviewer was from a different background, hence there wasn't any question-answer session
If there is a bowl of fruit and you are one fruit what fruit will you be and why.
Explain what you learned in this course (VHDL, design classes, object oriented programming, etc)
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