They asked about mu uvm design verification project
Design Verification Interview Questions
3,719 design verification interview questions shared by candidates
I can't remember much, but one question was on Finite State Machine for Traffic Lifgt control.
The first interview related to the introduction about both parties and a personality check of the candidate
Black-box vs white box testing, techniques used while verifying designs, system verilog constructs related to verification, UVM OVM etc
functional coverage, types of bins, types of array, constraint examples, virtual class,threads
Digital Logic, Computer Architecture, SystemVerilog, UVM, basic PERl
mux tree, FSM, Regions, NBA, DDR, Swapping of variables, crystal oscillator, full adder using 2x1 mux
Formal verification basics, writing assertions, etc.
Uvm related Project related Sv concepts Fifo full empty conditions Fork join concepts Axi ahb difference
Design an FSM and write Verilog code for an asynchronous fifo
Viewing 1881 - 1890 interview questions