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Digital Associate Interview Questions
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Digital IC design know how, coding.
Cross clock domain synchronization - Module A transmits @ 100 MHz and Module B accepts at 10 MHz. How will you manage the transactions?
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1st two interviewers : Volatile v/s Non Volatile memory (RAM/ROM) Basic Verilog questions like blocking v/s non-blocking, continuous vs procedural etc Explanation of all my FPGA/Verilog-related projects 2:1 MUX using basic gates Setup vs Hold, which is more important, why is it caused. metastability - how to fix it FIFO uses ASIC design flow How does synthesis happen Synchronisation vs Asynchronous clock 3rd Interviewer: Equation for power in a resistor Analysis of parallel LC circuit 2 i/p AND gate where each input is getting pwm of period 10. But on input B, an inverter of 1ms delay is attached. What's the resulting waveform? Is it practical to be used with a f/f Transfer characteristic of NOT gate Can NOT gate be used as an amplifier
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Sequence detector
1. Frequency divider circuits. 2. JK flip flop truth table and circuit gate based implementation. 3. Sequence detector using FSM for 00100 overlapping. 4. Usage of clock in sequential circuits. 5. setup and hold time. 6. How do you express frequency in terms of setup and hold times. 7. 1 aptitude question. (only this question not answered properly)
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