Q:Technical round they asked me to draw a Digital circuit with ousing only NAND gate.Then a FSM for 1101 and implememt it in Verliog later there were some branch out questions on FSM. Clock domain crossing was also asked and some questions(GATE Level) on setup and hod time violations.
Basic digital design knowledge like setup and hold time, clock domain crossing and something related to your thesis.
How to sort a list, how to use a mux to implement a logic gate
Q: Tell me about yourself
Do you familiar with UVM verification method？How's your script writing? (She asked nothing related to semiconductor or Integrated circuits).
Timing analysis, and how to reduce delay of combinational circuits
How do you verify a SoC system with multiple bus protocols?
Comment on the code below.... Some simple C code with lots of bugs is provided. They expect you to describe the function of the code and describe what each line/command does. The more description the better.
questions about CDC, STA, SPI/I2C interfaces, DSP logic
Basic questions, some technical. Lots of VHDL
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