Questions related to a verilog project I did in college.
Formal Verification Interview Questions
36 formal verification interview questions shared by candidates
You have a module that gets 4 input bits and returns the number of lower bits that are logic ‘1’, along with a valid bit. Expand it to 16 bits.
each interview had at least 3 RTL design questions
verify a FIFO using formal verification techniques and methods to resolve complexity
Linux: how to create a file, how to find all file that contain FOO, with case sensitive and case insensitive.
Look at these two statements: x, y are real finite number for all x, there exists a y such that y >x there exists a y such that for all x y >x 1) What is the difference between the two statements? 2) Do you think they are wrong ? Why ?
Discussed about verification projects in resume, how is formal and functional verification different. On coderpad, he gave an RTL code and asked to identify different scenarios and write SV properties of them. The RTL had a buggy FSM and asked me to debug it.
Q : Draw the FSM diagram for a given case considering mealey machine and taking the overlap cases.
1. basics of Verilog. 2. verification coding questions. 3. coding question in Verilog.
Medium assertions questions. They were related to grant
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