Setup time and hold time calculations of a design? Optimization of FPGA design interms of power, timing while makking frequency efficient.
Fpga Design Engineer Interview Questions
681 fpga design engineer interview questions shared by candidates
About what I did in different jobs that I had
Given this basic design interface, what things would you verify?
Programming project in Verilog language
Q: what is FIR/IIR and the difference between them
give a network package buffering design problem, just write code
They asked about my previous work. Asked about my interests for the future.
What is the output of this digital circuit?
Detail the difference between grey encoding standard encoding, and one hot
For the first test, you need to know the basic knowledge of digital design and some knowledge about system verilog and lookup table
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