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Fpga Design Engineer Interview Questions
681 fpga design engineer interview questions shared by candidates
Timing analysis and clock constraints
How would you improve timing on a 32 bit ripple carry adder?
Describe to me a in details about one of your latest projects.
Given a tree of 2-bit adders (no branching and looping), how would write an algorithm to reduce its over all delay?
Given two integer arrays, write a function which can compute the product of first array and save in the second array, except the product of that particular element from first array of same index you currently store in second array. A = [a(0), a(1), a(2), a(3) ... a(n)] B = [b(0), b(1), b(2), b(3) ... b(n)] where b(0) = a(1) x a(2) x a(3) .... x a(n) b(1) = a(0) x a(2) x a(3) .... x a(n) . . . b(n) = a(0) x a(1) x a(2) .... x a(n-1)
How does AHB bus start its transaction?
Work experience
They ask me some details about the project
General Digital Electronics and protocol based questions like AXI, UART, etc
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