describe the rtl flow in vlsi?
Fpga Engineer Interview Questions
681 fpga engineer interview questions shared by candidates
AND gate on fpga,fsm,sta commands.
Qué perfil tienes Qué flexibilidad Qué eres más de hardware o de software
My interview was for normal one, just like you have in any other company, they asked me about my work experience, technical background, academic qualification, why IMC, reason for quitting the current company, expected salary etc.
write RTL Code for PIPO, SISO, PISO, SIPO
What is a challenge you faced and how did you overcome it
5. What is the frequency of the MSB of 3 bit counter of frequency f hz 6.binary to hexa decimal conversion 01011010 7.. 625 in decimal to binary 8.two switches are at staircase connection for a bulb one switch in the first floor other in second floor...the operation of the bulb is based on which gate 9. A 3 bit counter with last gate connected to not and what is the range of counting Ans is 0000to 0101 10. Clipper circuit with zener parallel to apply and to obtain the output voltage waveform 12. A resistor circuit with all resistances are 1ohm...and current is 1amp. To find the voltage across a and b 13. Zener based circuit and to obtain output waveform with input sine wave given 14.which diode is on 15. Demux with logic 0utput... The logic 0outputs given to or gate and all inputs are inverted and obtain output function 16.a mux with 4inputs and 3inputs are high and one is inverted and output of mux given to logic low chip select.... The address range that can be accessed by the peripherals are 17.counter with each flip flop has Some ns delay and some ns setup delay.. What is the frequency of operation 18. Shift registers output after 2clocks serial in parallel out 19. What is the max and min values of 2s complement n bit number 20. Steady state response question 21. Frequency division one more question in counters
Design (block diagram) and write in hdl a feedback mechanism: inputs are Cartesian points and target point , output is the calibrated points with correction regarding the target point.
what is latch and flipflop
How to prototype low power logic such as clock gating in FPGA?
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