Typical clock domain crossing questions, DDR, FPGA timing analysis. Also wanted applicant to design a circuit over the weekend with testbench and results. I did not get to this point since the interviewer seemed more interested in having me describe verilog language constructs that I do not regularly use in the design of hardware circuits, maybe used in a testbench when I don't care about non-synthesizable code.
A waveform was given and we had to design a circuit for the same
advantages of FPGA over Controllers
What is the difference between blocking and non blocking assignments?
Did you work on any microprocessors earlier?
Describe what happens when you start your computer
Raccontaci di te, la tua esperienza, su cosa hai lavorato durante il tuo progetto di tesi.
amba protocol siso verilog code STA about mtech/btech project I2C
I was presented with a clock signal, an input signal, and an output signal and asked to design a system that would produce an output signal given such an input signal.
It was good mostly focused on basics?
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