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/* Design a module that takes a 1B input stream and converts it to a 32B output stream. Each stream has the signals valid, rdy and data. - Assume this is a single clock domain, reset is whatever you like - Assume that the input valid can toggle, and can stay low for any number of cycles - Assume that the rdy coming from the 32B side is always asserted to start din[0] = 0xff = clk 1 din[1] = 0xfe = clk 2 ... din[31] = 0xc0 = clk 32 dout[255:0] = 0xc0 ... 0xfe, 0xff, valid_out = 1 */
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Hardware Engineer

Interviewed at Amazon

3.5★
Apr 18, 2025

/* Design a module that takes a 1B input stream and converts it to a 32B output stream. Each stream has the signals valid, rdy and data. - Assume this is a single clock domain, reset is whatever you like - Assume that the input valid can toggle, and can stay low for any number of cycles - Assume that the rdy coming from the 32B side is always asserted to start din[0] = 0xff = clk 1 din[1] = 0xfe = clk 2 ... din[31] = 0xc0 = clk 32 dout[255:0] = 0xc0 ... 0xfe, 0xff, valid_out = 1 */

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