/* Design a module that takes a 1B input stream and converts it to a 32B output stream. Each stream has the signals valid, rdy and data. - Assume this is a single clock domain, reset is whatever you like - Assume that the input valid can toggle, and can stay low for any number of cycles - Assume that the rdy coming from the 32B side is always asserted to start din[0] = 0xff = clk 1 din[1] = 0xfe = clk 2 ... din[31] = 0xc0 = clk 32 dout[255:0] = 0xc0 ... 0xfe, 0xff, valid_out = 1 */
Explain a recent design and answer probing follow-up questions
Parallel Computer architecture, -Gave the MP structure and then asked How would you maintain coherency
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Have you ever done anything outside of your day to day tasks and responsibilities?
The question mostly related to your relevant experience as well as the skill required for the role.
Draw the components I would see in a PCB board and was asked why I drew the RAM slot closer to the CPU
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What was the most technical job you have worked on?
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