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5,134 hardware manager interview questions shared by candidates

Phone interview - 2 projects on resume, Mealy and Moore, FSM for a given sequence, basic cache related questions, setup hold, how to fix them, SRAM DRAM, SRAM full operation, Unix commands grep, chmod, chop, chomp, ps. Onsite - Round 1 - Behavioral round. He was an engineer at Intel for 22 years. But he mostly asked about my resume and behavioral questions. He wanted me to ask him a lot of questions. Round 2 - Lunch with 8 members of the team. Just casual discussion about Folsom and my school and work at Intel. Round 3 - Complete Physical Design. Starting from the flow, she asked me every aspect of it. What are inputs to floorplan? Will it help if these inputs are available at Synthesis stage itself? what is clock tree synthesis? why is it done after placing? timing questions. How is power structure decided at floorplan? voltage delay dependence, inverted temperature dependence, sizing of gates, CMOS fabrication process and diagram, layout for CMOS. Round 4 - Timing in more detail and more difficult questions, inverter vs buffer, SRAM layout, why higher metal for Vdd Gnd? Why resistance is lower for higher metal layers? spef saif formats, verification basics, reliability verification, functional verification. Round 5 - Perl questions. Gave a file and asked me to extract few details using regex. Then had to use hashes to perform some operations on the extracted data. basic C++ questions and simple programs.
avatar

Graphics Hardware Engineer

Interviewed at Intel Corporation

3.9★
Oct 2, 2015

Phone interview - 2 projects on resume, Mealy and Moore, FSM for a given sequence, basic cache related questions, setup hold, how to fix them, SRAM DRAM, SRAM full operation, Unix commands grep, chmod, chop, chomp, ps. Onsite - Round 1 - Behavioral round. He was an engineer at Intel for 22 years. But he mostly asked about my resume and behavioral questions. He wanted me to ask him a lot of questions. Round 2 - Lunch with 8 members of the team. Just casual discussion about Folsom and my school and work at Intel. Round 3 - Complete Physical Design. Starting from the flow, she asked me every aspect of it. What are inputs to floorplan? Will it help if these inputs are available at Synthesis stage itself? what is clock tree synthesis? why is it done after placing? timing questions. How is power structure decided at floorplan? voltage delay dependence, inverted temperature dependence, sizing of gates, CMOS fabrication process and diagram, layout for CMOS. Round 4 - Timing in more detail and more difficult questions, inverter vs buffer, SRAM layout, why higher metal for Vdd Gnd? Why resistance is lower for higher metal layers? spef saif formats, verification basics, reliability verification, functional verification. Round 5 - Perl questions. Gave a file and asked me to extract few details using regex. Then had to use hashes to perform some operations on the extracted data. basic C++ questions and simple programs.

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