For a square waveform at 10Ghz, what does display on a scope with the bandwidth of 5 GHZ
Hardware Manager Interview Questions
5,136 hardware manager interview questions shared by candidates
A 10 ua current source (with PMOS current mirror configuration) is connected to a variable resistor, plot the current value as the resistor value changes from 0 to infinity.
Questions related to pmos/nmos transistors. Discussion on holes/electon migration.
What is my experience with electronics design in the areas of sensors, signal conditioning, data acquisition, FPGAs, microcontrollers, and display devices.
A block diagram of a system was drawn on the whiteboard and 4 scenarios were described in which an aspect of the system was exhibiting an anomaly. I was asked to describe the likely cause of each anomaly.
1.Inverted temperature effect on STA. the question was based on temperature effects on delay below 65nm technology. how STA works under those conditions at different corners. 2. An interesting question about how latency affects jitter. 3. Maximums kew allowed when lock up latches are used. 4. OCV n questions based on it. 5. CRPR. 6. how does a cell get min n max delay? 7. spef file contents, questions about star-rd extractor working. 8. Internship exp based questions.
What's the difference between window and frame in tkiner?
Concepts related to D-to-Q delay, timing constraints of digital circuit design.
Basic Verilog and Digital Electronics questions, regarding project, C programming, System Verilog questions, puzzle questions, static timing analysis, hold and setup times, Computer architecture, python.
JK flip flops operation and timing diagram
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