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584 ic engineer interview questions shared by candidates

setup & hold time , its violation, causes and measures, my projects in detail, MIPS pipeline structure draw on whiteboard, stall and bypass logic implementation, arbiter design and implementation, risc vs cisc with examples, IP packet transmission and errors in it, how to resolve the error, verification basics and methods of testing, latency, ASIC vs Verilog RTL code difference.
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IC Design Engineer

Interviewed at Marvell Technology

4.3★
Jan 26, 2020

setup & hold time , its violation, causes and measures, my projects in detail, MIPS pipeline structure draw on whiteboard, stall and bypass logic implementation, arbiter design and implementation, risc vs cisc with examples, IP packet transmission and errors in it, how to resolve the error, verification basics and methods of testing, latency, ASIC vs Verilog RTL code difference.

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