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I am working on optimization of convolution engine for CNN's, i am giving the questions as far as i can remember q1. What is adder tree in verilog? q2. design a ckt to add 10 binary numbers using 5 adders in minimum clock cycles possible. can use any number of registers. q3. asked me to further optimize it. q4. questions on throughput and latency. q5. how can the dataflow be optimised for convolution in CNN's . conventional hr questions afterwards
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Research and Innovation

Interviewed at Tata Consultancy Services

3.5★
Nov 30, 2022

I am working on optimization of convolution engine for CNN's, i am giving the questions as far as i can remember q1. What is adder tree in verilog? q2. design a ckt to add 10 binary numbers using 5 adders in minimum clock cycles possible. can use any number of registers. q3. asked me to further optimize it. q4. questions on throughput and latency. q5. how can the dataflow be optimised for convolution in CNN's . conventional hr questions afterwards

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