DV team lead asked a question about mathematical proof for paired prime numbers characteristic.
Layout Engineer Interview Questions
427 layout engineer interview questions shared by candidates
Why is PMOS sub VDD and NMOS sub GND?
1. Difference between SystemVerilog and Verilog. 2. Difference between nonblocking and blocking. 3. Difference between asynchronous and synchronous. 4. How can you observe and solve the problem if there is a timing violation (related to setup time and hold time)
Describe the process for design of a new architecture and the refinement process
Why did you decide to apply for this role?
If you are done wit your work and the other guy is slower than you what would you do?
latch up
What is well proximity Effect
What is footer cell, what is it used for?
HR interview is the toughest one.
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