Logic Algorithms like FFE CTLE LTE mainly receiver type equalization and CDR
Logic Design Engineer Interview Questions
143 logic design engineer interview questions shared by candidates
build a device that get 3 bits. the first bit that was on will be the number in binary that will appear at the output until a reset will be pressed.
They gave me a design problem and kept on telling me to optimize it
Describe a relevant project and explain how you approach a problem
Computer Architecture
2:1 MUX, full adder, logic simplification, counter, FSM
I was asked to code an async FIFO.
Design a system that receives 4 inputs and outputs index of one hot
Behavior questions, questions about my research
5) Build inverter and buffer using XOR gate 6) Use of XOR as comparator 7) Floorplanning of simple 5 stage pipeline CPU. Some questions related to Work experience. Any questions for the interviewer.
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