Draw distributed memory system layout.
Logic Design Engineer Interview Questions
143 logic design engineer interview questions shared by candidates
What is inheritance? How do you design a D Flip Flop in SystemVerilog. What kind of state machines are there and what are the pros and cons of each. What is the behavior of a described HDL module.
1. assertion in system verilog 2. differences on task and function in system verilog 3. CMOS problems. 4. Capacitors are connected in series and parallel problems. find total capacitance, charge and voltage across the capacitors 5. What are generator clocks 6. diff between reg, wire and logic 7. detail on blocking and non blocking assignment 8. Inheritance concept in system verilog and how do you implement it 9. Explain full adder truth table (Please explain in words, I did a great blender by explaing line by line with numbers 10. virtual interfaces 11. how do you implement syncronous reset and asyncronous reset 10.
Please tell me about your current job/project involved
Final year project, digital logics and soft skills
3) Different ways to close timing 3b) Timing closure with gates of different W/L ratio. 3c) Timing closure with gates of different no of inputs. Advantages and Disadvantages.
Asked Data structures in Hardware Design role. So be prepared for it
2 Technical questions with regards to electrical components and logic gates.
A lot of questions on clock domain crossing.
All fairly easy programming question, but make sure your code is elegant and clean, while not taking too long to finish 6 hrs should be fair.
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