ff structure description with most detatils you can. it was kind of deep solution so I needed to understand all the pd considerations and et. was very very interesting. priority encoder questions and planning questions that I was aware of from my university studies.
How to apply what we learned from school to the current going on project? Some verilog coding questions. Basic logic design questions. More on the verilog project we did at school for a RISC processor.
Fifo depth calculation - different read and write frequency and burst size
Design of FIFO
See interview process, the questions are listed in there
You need to design a logic system with input of a stream of bits and it needs to detect a known chunk of bits, e.g. '1000'. First, implement a naive system. What are the inputs and outputs? Which logic gates, modules and blocks do you need? Analyze it with respect to timing, efficiency, hardware usage, etc. Second, try to come up with a more efficient implementation. Analyze it again. Compare the two implementations.
Explain pipelining, how did I implement it in my RISC microprocessor project
What is your weakness
Questions were from basic digital design (Flip flop, latch, MTTF etc), Computer architecture (Pipeline, Cache etc), basics of Verilog. The interviewer also about my graduate project and about my previous internship experience in detail. Interview went on for about 45 minutes. Overall good experience. The recruiter got back in touch after 10 days.
given a arbiter, a FIFO, 4 inputs, One flop how will you design a 4 stage pipeline structure.
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