How many harmonics are necessary to view a waveform on the scope?
Memory Design Engineer Interview Questions
151 memory design engineer interview questions shared by candidates
introduce your background and experience on your resume
When do you wash your hands?
What activities have you done?
5. Draw XOR using NAND only, with only 4 NAND gates.
1. Explain SRAM working and Noise margins of it. 2. How does PVT variation affect SRAM access times and NM. 3.Concept of Setup time and Hold time. How to fix it in Si validation. 4.Leakage current of MOSFET. How does it scale with Length, Vth and Temperature. Techniques to reduce leakage current of MOSFET (Multi Vt, DVFS, Body biasing, Header/Footer switch, Clock gating) 5. Where to use Header and Footer switch? Does FinFet has body biasing phenomenon to reduce leakage like conventional FETs. 6.Any experience with EM simulation, memory compiler design and Digital verification/STA.
Give an example of a supporter journey you have worked on
Present some recent relevant circuit work.
Draw a XOR gate with CMOS.
In depth technical questions ranging from basic VLSI, logic design, CMOS, physical design & Project & presentations
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