Layout of an inverter, Verilog coding for a state machine, physical design flow
Physical Design Engineer Interview Questions
3,254 physical design engineer interview questions shared by candidates
layout related questions, and generic cmos question
PNR flow, Sta, OCV, AOCV Internship experience based questions Physical verification and Routing
OCV related, Cross-talk related, timing analysis
Could not clear the screening test, therefore no HR round was conducted
was asked why 2 inverters are better that 1 buffer for fixing quality. and what the advantage of using 1 buffer that 2 inverters.
projects, setup / hold violation and mitigation, low power design, device physics
How to combine nmos and pmos with only one substrate?
Describe the transistor IV cruve
Make a CMOS inverter with MOSFETs
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