Physical Design Engineer Interview Questions

3,254 physical design engineer interview questions shared by candidates

how to solve setup violation? What the solution would impact on the other part of the design? how to deal with the SI issue? Clearly know about the calculation of setup time, or min clock period What is OCV on timing check?how to calculate? What is the CPPR?
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Physical Design Engineer

Interviewed at NVIDIA

4.4
Jun 4, 2017

how to solve setup violation? What the solution would impact on the other part of the design? how to deal with the SI issue? Clearly know about the calculation of setup time, or min clock period What is OCV on timing check?how to calculate? What is the CPPR?

1.Inverted temperature effect on STA. the question was based on temperature effects on delay below 65nm technology. how STA works under those conditions at different corners. 2. An interesting question about how latency affects jitter. 3. Maximums kew allowed when lock up latches are used. 4. OCV n questions based on it. 5. CRPR. 6. how does a cell get min n max delay? 7. spef file contents, questions about star-rd extractor working. 8. Internship exp based questions.
Nov 8, 2013

1.Inverted temperature effect on STA. the question was based on temperature effects on delay below 65nm technology. how STA works under those conditions at different corners. 2. An interesting question about how latency affects jitter. 3. Maximums kew allowed when lock up latches are used. 4. OCV n questions based on it. 5. CRPR. 6. how does a cell get min n max delay? 7. spef file contents, questions about star-rd extractor working. 8. Internship exp based questions.

1. Toughest question asked (in my opinion, as it required creativity and knowledge to answer) was on writing the following function in Verilog: W = .5X + .25Y Where W was an output, and X/Y are inputs. 2. If X/Y where 4 bits each, what is maximum output number possible?
avatar

Physical Design

Interviewed at NVIDIA

4.4
Sep 25, 2023

1. Toughest question asked (in my opinion, as it required creativity and knowledge to answer) was on writing the following function in Verilog: W = .5X + .25Y Where W was an output, and X/Y are inputs. 2. If X/Y where 4 bits each, what is maximum output number possible?

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