What is setup time and hold time? How would you fix these violations pre-silicon and post-silicon? What is the difference between clock skew, clock jitter, and clock uncertainty? Draw CMOS for a 1-input NOT gate, 2-input NOR gate, and 4-input NAND gate. Draw the circuit for a full-adder with minimal number of gates.
Describe how to build a flip-flop
What is floorplanning, partitioning, etc.
Phone screening 1. Questions about previous work experiences, digital circuit/layout design. 1:1 Technical interviews 1. RC circuits. Response to step input signal. 2. Transistor sizing for better setup/hold times. 3. Layout design of NAND3/NOR3 gates in different styles 4. Elmore delay of complex gates. 5. Standard cell library architecture choices and tradeoffs 6. Physical verification of standard cell libraries 7. DFM/DFD questions 8. Perl/Tcl and EDA tool related questions
what are the component of PLL uncertainties ? How would design datapath that cross clock domain?
Most questions were based on STA, timing and some based on PERL.
Explain Semi custom flow. STA. Layout verification related.
A few basic questions on Digital and wireless communications, estimation theory, random processes etc. Mostly questions based on work I had done before.
Basic pd questions, logical thinking
Flow of current in a layout ( given randomly by the interviewer)
Viewing 2191 - 2200 interview questions