when Capacitors in series or parallel what happens to charge and voltage
Physical Design Manager Interview Questions
3,254 physical design manager interview questions shared by candidates
What did you do on your project
Given a sequential Circuit with delays and asked about the frequency and slack of the circuit..?
STA, Synthesis Flow, Verilog code for divide by 3 clock, basic data structures, placement routing algorithms, Transistor models, equations of current in saturation mode, low power techniques, some behavioral questions.
the interviewer gave me scheme of two blocks, in the left block (block A) there were 2 FF, FFa and FFb. in block B there were only logic. FFa routed through logic to block B, and returned through logic to FFb in Block A. the interviewer tell me that is 150ns delay in the timing path between FFa and FFb, and ask me to describe what can be the cause and how to fix it.
What's constraints you gave to your design?
XOR with 2:1 MUX Edge detection Circuit Setup and hold time their violations Why do we need them what can you do to reduce them what would you do to correct s&h time after fabrication
How to resolve Placement congestion.
What is your ability to work in a team environment
What are your 5 year goals? What qualities do you think are important for a company to have?
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