1. Day 1 - Call from manager (30 minutes) -> He was very cool. So it wasn't that hard to deal with him :) -> He just went through some basic stuffs in my resume and then some technical questions.Some questions that I could recollect are the following. -> Can you explain the basic design flow of a system in FPGA? -> What kind of FPGA did I use in my project? ->If you get an new FPGA , what all components will you expect in that? -> Describe the basic hardware setup of FPGA in your lab. -> How would you debug a design in FPGA ? How can you probe to different interconnects in your design? -> Different components of a test bench. What level of simulations were done before generating the bit file and running the design on FPGA? -> What is PLI? - Programming Language Interface -> Difference between blocking and non blocking assignments, Fork and Join. Different methods in Verilog (always, initial block), How many times does an Initial Block gets executed. 2. Day 2 - Call from two tech leads of the team (1 hour) -> Even they started with my projects in resume. Some questions that I could recollect are; -> On what aspects of C have you worked on? What is the largest program that you have written in C? -> What do you think are the basic changes from C to C++? -> What do you mean by polymorphism in C++ ? -> Have you used any code debuggers in your projects? -> On what aspects of Perl have you worked on? You built the code from scratch or was that an incremental development? -> Basic components of a processor? -> Why we use cache in the processor? Difference between write back and write through policies? -> Can you think of a disadvantage of cache? -> If the goal of a design is minimize(area, delay,power), can you point out the compromise you would make in each of the following; area and delay, delay and power, power and area? -> Tell a situation you would have faced in your design experience : Tests passed in simulation but the synthesis failed. -> If you have an option to select between schematic and RTL, which one would you prefer. Why would you mix schematics and RTL in your design ? -> How would you save power by scaling down Vdd ? Will that affect the frequency of operation of your design ?What is the compromise you would make here? -> i have used Bloom filter in one of my projects, so they asked what is Bloom filter ? Why did you choose bloom filter when so many other hash functions are available out there? -> What do you mean by false positives in hash functions? -> Explain the design approach of an Inter Convertible FIFO, which could be used as a FIFO or as a Data Ram.
