Asked me in detail about phase noise in PLL
Rf Hardware Design Engineer Interview Questions
37 rf hardware design engineer interview questions shared by candidates
opAmp, MOS, Smith Chart matching, AM,, bode plot, basic small signal analysis, stability of circuit...
How would you reduce the size the the antenna
5mins English presentation and prepare one page slide before the interview
Smith chart basics. Intermodulation products. Digital modulation schemes and their BER. Opamps. Transistor basics. LNA and PA design questions.
Some basic telecommunication knowledge.
System of communication form TX to RX, detail and why?
RF PCB knowledge
detailed wireless standard question
Q: how will we setup a lineup? What are disadvantages if we use Filter as first stage. Q: What is EVM? Q: Scenario: Assume TX side gives B1UL output and RX is receiving B1DL/B3DL and B7DL. What parameters will you investigate? Q: Why does a device has nonlinearity? Q:worst return loss possible? Q: how would you match two points in smith chart? Which one would you choose among 4 types matching? Answer: first I will ask what BW is needed? Q: why do we want our system to be linear? What is intermod? How much intermod will increase with 1 dB increase in Pin? Channel leakage Q: How will you model non-linearity. You don’t have any data. Where does it come from? Q: how will you find IIP3? Q: how will you find noise floor of Spectrum Analyzer? Q: why do we see saw tooth noise floor at very low noise floor in Spectrum Analyzer? Q: how does line impedance change if you make it wider? How ideal line impedance can be expressed in terms of lumped model? Q: How does the wave travel in microstrip line? Which gnd do we want closer to coplanar microstrip line – gnd below the trace or the gnd on the same plane? Q: how will constellation diagram change if we 1. increase gain in I component. 2. Introduce Phase noise.
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