Rfic Design Engineer Interview Questions

82 rfic design engineer interview questions shared by candidates

Phone interview was about 15 to 20 questions in 45 minutes. I would most definitely recommend studying Razavi's 2nd edition analog design textbook whether you are applying for RFIC or Mixed Signal. Half of questions I was asked are on fundamental things starting from MOS transistors and device physics to Op amp design and Bandgap. The other half were on my specialties. If you are a PLL designer, you will be asked synthesizer questions. If you are an ADC designer, you will be asked ADC... and so on. Some of the questions that kept showing up through these interviews from both Qualcomm and other companies were the impedance transformation by MOSFET: what happens to the impedance of a resistor when it is in series with a MOSFET gate, drain, or source (source degeneration, input impedance of CG amplifier, CD amplifier, and so on). Bandgap will probably be asked. Impedance matching, if RFIC. I think that the outcome of the interview is highly dependent on the quality of the research presentation. If one claims to have done a design of such and such blocks, then one is expected to know pretty much everything about the block.
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Senior RFIC Design Engineer

Interviewed at Qualcomm

3.8
Mar 20, 2019

Phone interview was about 15 to 20 questions in 45 minutes. I would most definitely recommend studying Razavi's 2nd edition analog design textbook whether you are applying for RFIC or Mixed Signal. Half of questions I was asked are on fundamental things starting from MOS transistors and device physics to Op amp design and Bandgap. The other half were on my specialties. If you are a PLL designer, you will be asked synthesizer questions. If you are an ADC designer, you will be asked ADC... and so on. Some of the questions that kept showing up through these interviews from both Qualcomm and other companies were the impedance transformation by MOSFET: what happens to the impedance of a resistor when it is in series with a MOSFET gate, drain, or source (source degeneration, input impedance of CG amplifier, CD amplifier, and so on). Bandgap will probably be asked. Impedance matching, if RFIC. I think that the outcome of the interview is highly dependent on the quality of the research presentation. If one claims to have done a design of such and such blocks, then one is expected to know pretty much everything about the block.

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