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Rtl Design Engineer Interview Questions
272 rtl design engineer interview questions shared by candidates
They asked questions based on timing , skew, jitter and Digital Desgin. A Few questions based on relevant information in the your resume and other basic questions like such. Some python Data structure basics.
Edge detection circuit. Square root operation in Verilog.
None, everything was basic and expected.
I dint expect behavioral questions like, why should we hire you, tell me about yourself, what do your friends/prof/former employee say about you.
about SPI & I2C protocols and about academic projects
Write a verilog code for 1011 sequence detector ?
1.What are called verilog primitives in verilog?
They showed me a X-OR gate followed by a MUX. Input A and B was the direct input of the X-OR gate and the output of the X-OR gate was used as input to the MUX(0). A 0 was input to the 1 input line of the MUX. The input B was also used as the select line of the MUX. The question was: Like which gate the circuit will behave?
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