Clock divider circuit using verilog
Rtl Design Interview Questions
272 rtl design interview questions shared by candidates
Most of the questions required high problem solving skills: simple circuits (e.g. counter or circuits with adders, multipliers and multiplexers) which I had to design and/or modify in order to improve power consumption/latency/throughput
M.tech project and digital subject
How to design and write Verilog code for a synchronous FIFO
Verilog
what is metastable state in flipflop? what tool you have use for synthesis? what is setup time and hold time? how you can solve setup and hold violations?
Draw an OoO core and describe how it works
basic in Electronics side and digital electronics. he ask HDL language, clock domain crossing,DFT questions,Automatic test pattern generator and Basic FPGA questions.
About Digital Electronics, Verilog, C.
1st round - basic of digital electronics , basic of verilog , RTL basics , frequency divider fkt, flip flops and latches all the basic things about VLSI 2nd round- some basic technical discussion and about my project work
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