cross clock domain questions
Senior Asic Design Engineer Interview Questions
50 senior asic design engineer interview questions shared by candidates
asynchronous clock domain crossing, FIFO pointer logic, timing constraints, a divide by 3 clock generator
Problem on timing analysis
clock tree synthesis
What is your background?
Timing closure. How noise(cross-talk) affect setup/hold? How metal dimension affect timing?
7. Dual port RAM operation (if read and write req to the same location at a time?)
6. STA concepts
projects, basic asic questions
design async-fifo and sync-fifo in circuit level
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