Design a divide by 3 clock circuit
Senior Design Engineer Interview Questions
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How much experience in working on Block Level P&R. Describe Why Routing Required?
Difference between PN junction diode and Schottky diode
which projects i had worked before ? what was my working domain ? technical and management questions on how the issues and projects needs were handled ? why choosing tata technologies ?
Technical: PD Flow, PV, Timing concepts HR: Reason for change. Expectations in terms of work and career. Salary expectations
Questions on On chip variation and what causes them. Was asked how I'd model them. i mentioned timing derates -which are a very old technique. Was asked if i worked with AOCV models. Was asked few questions on clock jitter
Design a synch FIFO. Was asked a simplified version. Was asked to assume depth of FIFO was 4 and width was 32. He was just looking for how and when I'd update the memory buffer and the control logic for the free and avail Was given a verilog module and asked to figure out what it was doing. Noticed that it was a round robin-ish arbiter. Later was asked if there was any case where starvation (live lock) was possible. It became clear as I was working thru the waveforms there was a specific case where the arbiter can starve any of the requests. Then I was asked to fix the code. Also I was asked how would we catch issue like this. I mentioned that Formal Prop Verif tools are the best vehicles to find bugs on such designs
Describe your current role. Send a pulse from one clock to another clock. How to send data from one clock domain to another. Minimum sizing of an async FIFO
mosthy they asked about the previous experience,projects and verified the knowledge on those projects and baground verification.
4. How always @ (posedge reset or negedge clk) synthesized
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