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Verification Engineer Interview Questions
3,718 verification engineer interview questions shared by candidates
1. What is setup and hold time? Equation and analysis wrt latch and flipflop?
1. They asked me to explain a flip flop function with wave forms and an rtl programme in Verilog. 2. I was given a sequence of input waveform and was asked to design a state diagram and also to write an rtl code in Verilog 3. Functionalities of the Universal gates, clocking domains, STA, few analogue questions 4. To explain the previously done projects of my academic qualification in detail
For a six-deep FIFO with one (and two clocks), push and pop operations, what specific test cases will you use to verify the design?
ram,rom,hard disc,multiplier code in 8085,sta,maximum frequency
Can you work weekends?
Are you experienced with Outlook?
What should be taken care of first? Set-up or Hold Time
Tell me a time that you handled a difficult sitation
Do you know how to write and read test scripts
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