Design FSM for sequence detector
Verification Engineer Interview Questions
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Q: SystemVerilog syntax questions Q: Design a clock in verilog without any existing clock signals Q: Some flip-flop/latch design questions at clock-domain crossing.
1. why use OOP 2. comp arch question 3. logic design
comp arch. pipeline. etc
What are the stages in the pipeline?
Imagine if there was a word-file with a random word printed per line, how would you design a program that can parse through it and return the word with the amount of occurrences?
What is "wire" in System Verilog?
what value the interviewee could supply to the company?
If you had to add cache in the pipeline stage, where would you add it?
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