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3,718 verification engineer interview questions shared by candidates

Why NAND gate realization is preferred in digital design even though we can design complete circuitry using NOR gate also? Why we study sinusoidal response of a system however we know actual input to a system may be any signal? Why we need active filters even though we can design filters by using passive components only ? Why PMOS is used as Pull up network and NMOS is used as pull down network in CMOS logic implementation. Why Minority charge carriers available at the edge of depletion layer contributes in reverse current effectively and other charge carriers are ineffective?? Why slope=-1 point is considered for Noise Margin calculations in CMOS?? What is Barkhausen criteria for oscillaton Why Astable Multivibrator is called Square Wave Generator and why not Schmitt trigger ?
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Analog Mixed Signal (AMS) Verification Engineer

Interviewed at Microchip Technology

3.6★
May 28, 2024

Why NAND gate realization is preferred in digital design even though we can design complete circuitry using NOR gate also? Why we study sinusoidal response of a system however we know actual input to a system may be any signal? Why we need active filters even though we can design filters by using passive components only ? Why PMOS is used as Pull up network and NMOS is used as pull down network in CMOS logic implementation. Why Minority charge carriers available at the edge of depletion layer contributes in reverse current effectively and other charge carriers are ineffective?? Why slope=-1 point is considered for Noise Margin calculations in CMOS?? What is Barkhausen criteria for oscillaton Why Astable Multivibrator is called Square Wave Generator and why not Schmitt trigger ?

Basic digital, verilog questionscan be answered if you know the concepts well, Sv was totally into randomization , coverage and assertions. Uvm basic things initial rounds and in depth in last round. In manager round all digital, verilog, sv and uvm were covered
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Design Verification Engineer

Interviewed at Micron Technology

3.9★
Dec 19, 2020

Basic digital, verilog questionscan be answered if you know the concepts well, Sv was totally into randomization , coverage and assertions. Uvm basic things initial rounds and in depth in last round. In manager round all digital, verilog, sv and uvm were covered

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