We want to send a specific amount of data and to prevent errors, we want to divide the data into several segments randomly within a certain size range. How can we perform this division so that there will definitely be enough data for all the remaining packets?
first was an assembly question, to implement multiplication with certain commands and few registers avaliable. second question was to build a xor gate with 4 wierd components which are sometimes Z and sometimes have output.
CDC, HW design, testbench engineering, etc..
Had to write a verilog code for some handshaking protocol.
Setup/hold time problem; meta-stability; 5-stage pipeline
Implement a circuit board the receives an 8-bit bus. The output is an 8-bit bus where the first net that is '1' in the input is also '1' in the output, the rest are '0' (in other words - "find first '1' in the input bus).
General questions in Python, C, Verilog, and SystemVerilog.
UVM Phases, why do we use Virtual, Constraints , Use of randc , assertions , how do you override , how do you analyze verification metrics, callbacks
How to use muxes to implement an XOR gate?
coding questions consists of - creating sequences - creating constraints for a given problem - creating an algo for data query
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