What is coherency, consistency, difference. How do you ensure them, protocols, practices. How do you verify them (project related stuff). Questions on UVM, SystemVerilog and Verilog
Verification Engineer Interview Questions
3,719 verification engineer interview questions shared by candidates
SV UVM knowledge DV knowledge Qs on RTL GLS IP specific questions background and asking to debug a piece of code
Why would you like to do this kind of a job?
why do we need factory registration in UVM testbench
How can you use your skill set in (the position you are applying for)?
OSI model Protocols in network layers Basic OS,DBMS,Java questions Questions based on Resume
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Difference between logic and reg? Difference between static casting and dynamic casting? resouce db and its significance? What is throughput rate? event scheduler in SV? UVM objections? Driver sequence handshake?
What qualities do you bring to the table?
1: what is set up and hold time?
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