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Verification Engineer Interview Questions
3,719 verification engineer interview questions shared by candidates
In first round basic timing questions related to setup and hold time, Object oriented programming concepts and basic scripting etc. In second round one design problem and cross questions on it.
C++ code for fibonacci series
Lot of linux command questions. Was asked to write many scripts.
basic questions about C, FSM, linux
1.About projects. 2.Digital electronics fundamentals like STA etc. 3.Simple verilog questions. 4.Some concepts of computer architecture and system verilog
RTL design questions, UVM questions
Verilog, digital electronics, fsm, vivado, fpga design, stages in asic design
1. write assetions to find the numers which are 2 powers.ex 2^0,2^1.....? 2.design counters for different scenarios like desing mod 15 counter but it should skip counting 0,3,4,8,5
Draw simple NMOS current mirror. what are its disadvantages and how do you overcome it . what is the new topology and swing across output node. and another topology if you have any problem with current topology. they asked sinking current mirrors too
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