Programming, queries, test cases, aptitude
Verification Engineer Interview Questions
3,719 verification engineer interview questions shared by candidates
Describe coverage types, describe comlexity of environmentst that you work so far, UVM reg model
given some waveforms , draw circuit
Nothing unexpected
Questions mostly about the project. Basics of Pcie protocol
Question about digital design and system verilog and uvm related questions
About me, school projects and all content in CV. Communication protocols and signal analysis Algoriths known
Setup and Hold Time Violations
about UVM, explain project (it was on UVM) , basic object oriented concepts like abstraction, constructor, function overloading
HR interview were standard questions. Interview with manager were more technical and based on testing and previous experiences
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