1. Overall was on project 2. UVM methodologies and SV 3. Have been asked on logical reasoning 4. Queries on verilog, RTL coding were asked. 5. OOPS based concepts ,Polymorphism, Inheritance, Arrays methods, stacks ,Queues, Multidimensional arrays ,Vectors
Verification Engineer Interview Questions
3,719 verification engineer interview questions shared by candidates
FIFO, LIFO in Verilog
What's a class, object? What does the .this operator? What are the types of FSM? What is the Grey code? Which are the components of a microcontroller? What's an interrupt? Which are the differences between RAM and ROM memories?
It gets very technical ranging from Electrical fundamentals to RF fundamentals and then they start to dig deep on each aspect. Know your chip caps really well! I was asked questions on smith charts, imedance matching, typical RF receiver/transmitter systems, signal integrity issues, characteristics of RF amps. As far as behavioral questions were concerned - challenges faced in your last project, how did u solve it and what would your ex boss say about you if I asked him for a reference.
Describe a color to a blind person.
Where do you see yourself in 5 years?
Why should i be hiered?
Algorithm from a published article and explain what this algorithm do.
System verilog,uvm,verilog constraints and assertions , about projects
Lcm, Swap, Factorial for C coding Write constraints in system verilog
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