1. Sv, uvm environment question 2. Coding of UVM architecture 3. Digital electronic 4. AMBA protocol
Verification Engineer Interview Questions
3,719 verification engineer interview questions shared by candidates
Why did you choose Texas Oncology?
FIFO coverage implementation in sv
D flip flop and its working and basic gate coding's
Why do you want to switch to automation instead of development?
Have you use Polarion, DOORS management tools? Do you know Python? Are you fimilar with ARP4754A, DO-178C?
They asked Digital questions, verilog
Basic questions on Digital electronics and C programming.
Basic digital design Verilog Python Digital verification concepts
Difference between virtual sequencer & virtual sequence.
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