Digital electronics,Static Timing Analysis, Verilog
Verification Engineer Interview Questions
3,719 verification engineer interview questions shared by candidates
Simple questions on verilog and system verilog.
Digital design verilog etc etc etc
Associative array, coverage, randomization, ahb offset address.
If two capacitors charged upto diifferent voltages were connected in parallel, what would be the voltage when measure across each?
DO178, Testing concepts, Verification and validation concepts.
She asked if I was good with people, because they get a lot of disgruntled customers.
Write Polymorphism code , Project discussion
when do you submit report to customer ?
Almost all questions were about my applied experience on verification. What kind of projects was I involved in. How would I handle a project under stress or time limits.
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