it was not that difficult.
Verification Engineer Interview Questions
3,719 verification engineer interview questions shared by candidates
Covered the resume.
All the questions were pretty basic and were related to fundamentals of logic design and verification.
Describe how CAM (content addressable memory) works.
Identify the circuit that the given FSM corresponds to, timing based questions, optimize the circuit. FSM was that of a simple counter
What challenges do you see in a cross-team effort for a verification project?
Know everything in c++. Virtual functions/class. Polymorphism. Be ready to write code on the spot
They gave me a design problem and kept on telling me to optimize it
UVM related questions.How to verify some components.How to verify a an old machine .X and Y dimensions of the screen in pixel was given.Was asked to write the test cases for the same.Was asked to a draw a fsm for a for traffic light signal .Questions related to clock skew,randomization and sorting algorithms
Draw the truth table for a NAND gate.
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