Timing diagram out put and combinational circuit output
Verification Engineer Interview Questions
3,716 verification engineer interview questions shared by candidates
how would you delete an object in SV? what happens when you assign a parent to child? Explain UPF and what we can accomplish using it?
How would you count the number of objects you created for a particular class?
State Machine, Verilog code writing
SV and UVM and the lastest projects
How are you generating clock in verilog, difference between fork-join and begin-end
FSM diagram of sequence detector and write verilog code
Difference between strobe and monitor?
1. Write a program to find prime numbers in between 2 to 100 2. Verilog code for frequency divided by 5 circuit 3. Verilog code for generic full adder 4. To find errors in a c code based on static type
System verilog and uvm related questions
Viewing 2721 - 2730 interview questions