Verification Engineer Interview Questions

3,713 verification engineer interview questions shared by candidates

Draw internal cmos crcuit for nand, nor gates. Bandwidth of opamps. Solve basic opamp circuits. They focus more on fundamentals of both analog and logic design. Also focussed on vhdl as it was used a lot for modeling in that group.
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Verification Engineer

Interviewed at Texas Instruments

3.8
Mar 19, 2016

Draw internal cmos crcuit for nand, nor gates. Bandwidth of opamps. Solve basic opamp circuits. They focus more on fundamentals of both analog and logic design. Also focussed on vhdl as it was used a lot for modeling in that group.

Make an AND gate from a 2-to-1 mux and make a k-map for that set-up, write code (any language) to arrange a N-sized list of numbers in ascending or descending order, what is set time, hold time, and metastability, divide a clock signal by three
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Design Verification Intern

Interviewed at Texas Instruments

3.8
Nov 10, 2024

Make an AND gate from a 2-to-1 mux and make a k-map for that set-up, write code (any language) to arrange a N-sized list of numbers in ascending or descending order, what is set time, hold time, and metastability, divide a clock signal by three

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