Previous project based questions Work Motivations Basic Engineering questions like Wireless technologies, SMPS, Power consumption etc
Verification Engineer Interview Questions
3,713 verification engineer interview questions shared by candidates
1. Constraint random, assertions, UVM env 2. OOPS concept 3. Coverage, python scripting 4. Verilog and digital logic
FSM for sequence detector. Verification environment. Verilog programming.
How to set config_cb from lower to higher hierarchy
I can't say exactly but one SystemVerilog question was to implement a finite state machine given a certain output. Review sequence detectors.
OOPs questions and also ASIC and Verfication based questions
Is program counter a physical memory address or a virtual address?
How to design a UVM testbench for a given design. What all componets are needed etc. Corner cases to test out and efficient way to build environment
Why Qualcomm?
question around the system verilog ,verification methodology.
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