C++, SystemVerilog basics
Verification Engineer Interview Questions
3,713 verification engineer interview questions shared by candidates
how to impliment A=7.5B w/o using *, /
Some question related to accessing analysis ports in a sequence ( via sequencer)
Basic computer architecture questions, pipeline concepts and hazards. FSM for a sequence detector. Fibonacci using recursion and linked list reversal. Some scripting question which i could not answer.
Confidential. But related to system verilog and uvm.
How many times does the clock hands cross each other throughout the day?
remove duplicates from array in place
Describe your previous projects and describe your contribution in them
Scripting questions on 2D hashes and asked for coding in perl/python. Basic questions on STA
Create an FSM for detecting a sequence
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