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Verification Engineer Interview Questions
3,713 verification engineer interview questions shared by candidates
Q1. FIFO depth, given read and write rates for a burst of x writes Q2. a=0; b=0; c=1; #1 a=c; #1 b =a; (Give waveforms) Q3. a<=0; b<=0; c<=1; #1 a<=c; #1 b< =a; (Give waveforms) Q4. a=0; b=0; c=1; a= #1 c; b=#1 a; (Give waveforms) Q5. a<=0; b<=0; c<=1; a<= #1 c; b<=#1 a; (Give waveforms) Q6. You have incoming bit stream. You can't store them. You get a new bit at every clock edge, find modulo 5 of the updated number everytime. Eg, if bitstream is 10111, you find modulo of 1, then 10, then 101 and so on..
Describes one of your projects
what is the process flow of design a chip in innovus
Write TB for one of the projects from past experience . Describe its features and implement DUT interface connections and build TB on whiteboard .
What is polymorphism explain with an example?
Pipelining, latency and throughput, Cache, types of cache, problem on set way associative cache, interrupts, Virtual memory, page fault, project.
Draw distributed memory system layout.
Implementing MIPS using pipelining
DV related, protocols, sv, uvm, axi,abp
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