difference of Union and Struct (C++). VIPT cache.
Verification Engineer Interview Questions
3,713 verification engineer interview questions shared by candidates
How to do the formal verification for a given module
pipeling and harzard.
design an electrical circuit with switches, voltage source for a particular application- wasn't expecting one since my area of expertise is mostly digital
I don't think the questions are difficualt. Some coding related questions I didn't answered well, mainly because my passed experiences are more focusing on the hw design, not sw coding.
2 signals, both only toggle once. At the first rising edge, start testbench; At the second falling edge, stop testbench. How?
Memory Consistency
MOSEI protocol. Cache hierarchy.
Design clock gating in system verilog. Difference between verilog and system verilog.
Design an FSM for a 2-clock system
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